The present invention claims the benefit of Korean Patent Application No. P2001-32476 filed in Korea on Jun. 11, 2001, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a fail repair circuit of a nonvolatile ferroelectric memory device and a method for repairing the same.
2. Background of the Related Art
Generally, a nonvolatile ferroelectric memory, i.e., a ferroelectric random access memory (FRAM) has a data processing speed equal to a dynamic random access memory (DRAM) and retains data even in power off. For this reason, the nonvolatile ferroelectric memory has received much attention as a next generation memory device.
The FRAM and DRAM are memory devices with similar structures, but the FRAM includes a ferroelectric capacitor having a high residual polarization characteristic. The residual polarization characteristic permits data to be maintained even if an electric field is removed.
FIG. 1 shows hysteresis loop of a general ferroelectric. As shown in FIG. 1, even if polarization induced by the electric field has the electric field removed, data is maintained at a certain amount (i.e., d and a states) without being erased due to the presence of residual polarization (or spontaneous polarization). A nonvolatile ferroelectric memory cell is used as a memory device by corresponding the d and a states to 1 and 0, respectively.
A related art nonvolatile ferroelectric memory device will now be described. FIG. 2 shows a unit cell of a related art nonvolatile ferroelectric memory.
As shown in FIG. 2, the related art nonvolatile ferroelectric memory includes a bitline B/L formed in one direction, a wordline W/L formed to cross the bitline, a plate line P/L spaced apart from the wordline in the same direction as the wordline, a transistor T with a gate connected with the wordline and a source connected with the bitline, and a ferroelectric capacitor FC. A first terminal of the ferroelectric capacitor FC is connected with a drain of the transistor T and a second terminal is connected with the plate line P/L.
A redundancy algorithm of the related art nonvolatile ferroelectric memory device will now be described with reference to FIG. 3.
As shown in FIG. 3, a full address memory test and a fail bit analysis are carried out in such a manner that a chip test is carried out after a prior process to find out a fail address.
When the analyzed fail address can be repaired by a row repair circuit, a fuse is cut using a laser beam to code a corresponding address in a row repair fuse block.
Once the corresponding fail address is input after the fuse cutting is completed, an active signal of the repair circuit is generated to activate a repair cell.
Meanwhile, a main cell corresponding to the fail address is inactivated by an inactive signal of the repair circuit.
Therefore, the main cell of a corresponding fail address is inactivated while the repair cell is activated.
The aforementioned related art method for repairing a fail address of a nonvalitile semiconductor memory device has several problems.
If a fail bit is generated, the analysis step of the fail bit is additionally required. In this case, a problem arises in that the redundancy algorithm becomes complicate. For this reason, there is limitation in reducing the redundancy time.
Furthermore, since the fuse is cut using the laser beam to repair the failed cell, it is difficult to change or add the redundancy algorithm at any time.
Accordingly, the present invention is directed to a fail repair circuit of a nonvolatile ferro electric memory device and a method for repairing the same that substantially obviates one or more problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a fail repair circuit of a nonvolatile ferroelectric memory device and a method for repairing the same, in which a redundancy time can be reduced.
Another object of the present invention is to provide a fail repair circuit of a nonvolatile ferroelectric memory device and a method for repairing the same, in which a redundancy algorithm can be changed or added at any time.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a fail repair circuit of a nonvolatile ferroelectric memory device having a repair logic unit therein, the fail repair circuit includes: a memory test logic block generating a redundancy active pulse (RAP) if a row address including a fail bit to be repaired is found during test; a power-up sensor generating a power-up pulse if a stable power source voltage is sensed; a first redundancy control block generating first to fifth control signals ENN, ENP, EQN, CPL, and PREC and a sixth control signal ENW in response to the RAP and the power-up pulse; a counter generating n bit counter bit signal increased by one bit through the RAP to correspond to the number of redundancy bits; a redundancy counter decoding control block generating an activated coding signal ENW less than n greater than  in response to the counter bit signal of the counter and the sixth control signal ENW; and a redundancy coding block outputting a master signal in response to the coding signal ENW less than n greater than  and the first to fifth control signals, programming a fail address in a plurality of redundancy coding cells, and outputting seventh and eighth control signals REN less than n greater than  and RPUL less than n greater than  to repair the programmed fail address.
In another aspect of the present invention, in a method for repairing fail of a nonvolatile ferroelectric memory device having a repair logic unit therein, the method includes the steps of: generating a redundancy active pulse (RAP) if a row address including a fail bit to be repaired is found during test; generating a power-up pulse if a stable power source voltage is sensed; generating first to fifth control signals ENN, ENP, EQN, CPL, and PREC and a sixth control signal ENW in response to the RAP and the power-up pulse, the first to fifth control signals controlling a redundancy coding block and the sixth control signal controlling a redundancy counter decoding control block; generating n bit counter bit signal increased by one bit through the RAP to correspond to the number of redundancy bits; generating an activated coding signal ENW less than n greater than  corresponding to the fail bit in response to the counter bit signal of the counter and the sixth control signal ENW; programming a fail bit(address) in the redundancy coding block including a redundancy master cell and a redundancy coding cell, each having ferroelectric capacitors, in response to the first to fifth control signals ENN, ENP, EQN, CPL, and PREC and the activated coding signal ENW less than n greater than ; and outputting seventh and eighth control signals REN less than n greater than  and RPUL less than n greater than  to repair the programmed fail address.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.